The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to methods and apparatus for monitoring a metal layer during chemical mechanical polishing.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a “standard” pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
One problem in CMP is determining whether the polishing process is complete, i.e., whether a substrate layer has been planarized to a desired flatness or thickness, or when a desired amount of material has been removed. Overpolishing (removing too much) of a conductive layer or film leads to increased circuit resistance. On the other hand, underpolishing (removing too little) of a conductive layer leads to electrical shorting. Variations in the initial thickness of the substrate layer, the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. These variations cause variations in the time needed to reach the polishing endpoint. Therefore, the polishing endpoint cannot be determined merely as a function of polishing time.
One way to determine the polishing endpoint is to remove the substrate from the polishing surface and examine it. For example, the substrate can be transferred to a metrology station where the thickness of a substrate layer is measured, e.g., with a profilometer or a resistivity measurement. If the desired specifications are not met, the substrate is reloaded into the CMP apparatus for further processing. This is a time-consuming procedure that reduces the throughput of the CMP apparatus. Alternatively, the examination might reveal that an excessive amount of material has been removed, rendering the substrate unusable.
More recently, in-situ monitoring of the substrate has been performed, e.g., with optical or capacitance sensors, in order to detect the polishing endpoint. Other proposed endpoint detection techniques have involved measurements of friction, motor current, slurry chemistry, acoustics and conductivity. One detection technique that has been considered is to induce an eddy current in the metal layer and measure the change in the eddy current as the metal layer is removed.
Another reoccurring problem in CMP is dishing of the substrate surface when polishing a filler layer to expose an underlying layer. Specifically, once the underlying layer is exposed, the portion of the filler layer located between the raised areas of the patterned underlying layer can be overpolished, creating concave depressions in the substrate surface. Dishing can render the substrate unsuitable for integrated circuit fabrication, thereby lowering process yield.